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never stop thinking. power management & supply d atasheet, v 2.0, 31 july 2003 pwm-qr ic tda 16846/16846-2 tda 16847/16847-2 controller for switch mode power supplies supporting low power standby and power factor
tda 16846/tda 16846-2/tda 16847/tda 16847 revision history: current version: 2003-07-31 previous version data sheet tda 16846: 2000-01-14 previous version data sheet tda 16846-2: 2002-07-30 page (in previous version) 20 21 22 23 page (in current version) 20 21 22 23 subjects (major changes since last revision) the data sheets for tda 16846 and tda 16846-2 have been combined in this version. some measuring values are updated: pin 1 basic value 1 v 1b1 and v 1b2 slightly changed. pin 2 discharge current i 2dc min changed from 0.5 ma to 0.6 ma. pin 14 overvoltage v 14ovmax threshold changed from 17.0 v to 17.1 v. pin 3 delay to switch on t 3d slightly decreased. pin 4 charge current i 4ch and discharge current i 4dch added. pull high resistor r 1min changed from 18kohm to 15 kohm according to the data sheet for tda 16846. pin 7 charge current i 7 min and upper threshold v 7hmin small changed. pin 13 rise and fall time adapted according to c 13 = 1nf (prev. 10 nf). v 13aclow slightly decreased (only tda 16846-2, tda 16847-2). tda 16846-2/tda 16847-2: improvements of tda 16846-2/tda16847- 2 compared with tda 16846/tda16847 pin 5 oci expanded input voltage range down to zero, series resistor between pin 5 and ground is no longer necessary. pin 7 syn improved startup to prevent the transformer from saturation also in fixed frequency and synchronized mode. pin 11 pvc noise-immunity improved by spike blanking. pin 13 out reduced output voltage level for off state. pin 14 vcc noise-immunity improved by spike blanking. edition 07.03 published by infineon technologies ag st.-martin-strasse 53 d-81541 mnchen ? infineon technologies ag 2003 all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as warranted characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, des criptions and charts stated herein. infineon technologiesis an approved cecc manufacturer. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologi es office in germany or our infineon technologies representatives worldwide. warnings due to technical requirements components may contain dangerous substances. for information on the types in question please cont act your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infin eon tech- nologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system , or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
version 2.0 3 31 jul 2003 controller for switch mode power supplies supporting low power standby and power factor correction tda 16846/16846-2 tda 16847/16847-2 bipolar ic p-dso-14-3 p-dip-14-3 1overview 1.1 features ? line current consumption wit h pfc low power consumption stable and adjustable standby frequency very low start-up current soft-start for quiet start-up free usable fault comparators synchronization and fixed frequency circuits over- and undervoltage lockout switch off at mains undervoltage temporary high power circuit (only tda 16847-2) mains voltage dependent fold back point correction continuous frequency reduction with decreasing load adjustable and voltage dependent ringing suppression time 1.2 description the tda 16846-2 (this name is used in the description for all types) is optimized to control free running or fixed frequency flyback converters with or without power factor c orrection (current pum p). to provide low po w er consumption at light loads, this device reduces the switching frequency in small steps with load, towards an adjustable minimum (e. g. 20 khz in standby mode). additionally, the startup current is very low. to avoid switching stress on the power devices, the power transistor is always switched on at minimum voltage. a special circuit is implemented to avoid jitter. the device has type ordering code package tda 16846 q67000-a9377 p-dip-14-3 tda 16847 q67000-a9378 p-dip-14-3 tda 16846g q67006-a9430 p-dso-14-3 tda 16847g q67006-a9412 p-dso-14-3 tda 16846-2 q67040-s4494 p-dip-14-3 tda 16847-2 q67040-s4496 p-dip-14-3 tda 16846-2g q67040-s4495 p-dso-14-3 tda 16847-2g q67040-s4497 p-dso-14-3
tda 16846/16846-2 tda 16847/16847-2 version 2.0 4 31 jul 2003 several protection functions: v cc over- and undervoltage, mains undervoltage, current limiting and 2 free usable fault comparators. regulation can be done by using the internal error amplifier or an opto coupler feedback (additional input). the output driver is ideally suited for driving a power mosfet. fixed frequency and synchronized operation are also possible. the tda 16846-2 is suited for tv-, vcr- sets, sat receivers and other sets for consumer electronics. it also can be used in pc monitors. the tda 16847-2 is identical with tda 16846-2 but has an additional power measurement output (pin 8) which can be used as a temporary high power circuit. figure 1 pin configuration (top view) 1.3 pin definitions and functions pin symbol function 1 otc off time circuit 2 pcs primary current simulation 3 rzi regulation and zero crossing input 4 src soft-start and regulation capacitor 5 oci opto coupler input 6 fc2 fault comparator 2 7 syn synchronization input 8 n.c./pmo not connected (tda 16846-2) / pmo (tda 16847-2) 9 ref reference voltage and current 10 fc1 fault comparator 1 11 pvc primary voltage check 12 gnd ground 13 out output 14 vcc supply voltage
tda 16846/16846-2 tda 16847/16847-2 version 2.0 5 31 jul 2003 1.4 short description of the pin functions pin function 1 a parallel rc-circuit between this pin and ground determines the ringing suppression time and the standby-frequency. 2 a capacitor between this pin and ground and a resistor between this pin and the positive terminal of the primary electrolytic capacitor quantifies the max. possible output power of the smps. 3 this is the input of the error amplifier and the zero crossing input. the output of a voltage divider between the control winding and ground is connected to this input. if the pulses at pin 3 exceed a 5 v threshold, the control voltage at pin 4 is lowered. 4 this is the pin for the control voltage. a capacitor has to be connected between this pin and ground. the value of this capacitor determines the duration of the softstart and the speed of the control (primary regulation). 5 if an opto coupler for the control is used, its output has to be connected between this pin and ground. the voltage divider at pin 3 has then to be changed, so that the pulses at pin 3 are below 5 v. 6 fault comparator 2: a voltage > 1.2 v at this pin stops the smps (v.also pin 9). 7 if fixed frequency mode is wanted, a parallel rc circuit has to be connected between this pin and ground. the rc-value determines the frequency. if synchronized mode is wanted, sync pulses have to be fed into this pin. 8 tda 16846-2: not connected. tda 16847-2: this is the power measurement output of the temporary high power circuit. a capacitor and a rc-circuit has to be connected between this pin and ground. 9 output for the reference voltage (5 v). with a resistor between this pin and ground the fault comparator 2 (pin 6) is enabled. 10 fault comparator 1: if a voltage > 1 v is applied to this pin, the smps stops. 11 this is the input of the primary voltage check. the voltage at the anode of the primary electrolytic capacitor has to be fed to this pin via a voltage divider. if the voltage of this pin falls below 1 v, the smps is switched off. a second function of this pin is the primary voltage dependent fold back point correction (only active in free running mode). 12 common ground. 13 output signal. this pin has to be connected via a series resistor to the gate of the power transistor. 14 connection for supply voltage and startup capacitor. after startup, the supply voltage is produced by the control winding of the transformer and rectified by an external diode.
tda 16846/16846-2 tda 16847/16847-2 version 2.0 6 31 jul 2003 1.5 block diagrams figure 2 tda 16846-2
tda 16846/16846-2 tda 16847/16847-2 version 2.0 7 31 jul 2003 figure 3 tda 16847-2
tda 16846/16846-2 tda 16847/16847-2 version 2.0 8 31 jul 2003 2 functional description start up behaviour (pin 14) when power is applied to the chip and the voltage v 14 at pin 14 ( v cc ) is less than the upper threshold ( v on ) of the supply voltage comparator (svc), then the input current i 14 will be less than 100 ()( ) ( ) ( ) ( ) () , ,, ( ),() (,)
tda 16846/16846-2 tda 16847/16847-2 version 2.0 9 31 jul 2003 figure 5 startup volta ge diagram primary current simulation pcs (pin 2) / current limiting a voltage proportional to the current of the power transistor is generated at pin 2 by the rc-combination r 2 , c 2 ( figure 4 ). the voltage at pin 2 is forced to 1.5 v when the power transistor is switched off and during its switch on time c 2 is charged by r 2 from the rectified mains. the equation of v 2 and the current in the power transistor ( i primary ) is : l primary : primary inductance of the transformer the voltage v 2 is applied to one input of the on time comparator ontc (see figure 2 ). the other input is the control voltage. if v 2 exceeds the control voltage, the driver switches off (current limiting). the maximum value of the control voltage is the internal reference voltage 5 v, so the maximum current in the power transistor ( i mprimary ) is : the control voltage can be reduced by either the error amplifier ea (current mode regulation), or by an opto coupler at pin 5 (regulation with opto coupler isolation) or by the voltage v 11 at pin 11 (fold back point correction). v 2 1,5 v l primary i primary r 2 c 2 ------------------------------- - + = i mprimary 3,5 v r 2 c 2 l primary -------------------------------------- =
tda 16846/16846-2 tda 16847/16847-2 version 2.0 10 31 jul 2003 fold back point correction pvc (pin 11) v 11 is derived from a voltage divider connected to the rectified mains and reduces the limit of the possible current maximum in the power transistor if the mains voltage increases. i.e. this limit is independent of the mains (only active in free running mode). the maximum current ( i mprimary ) depending on the voltage v 11 at pin 11 is : off-time circuit otc (pin 1) figure 6 shows the off-time circuit which determines the load dependent frequency curve. when the driver switches off ( figure 7 ) the capacitor c 1 is charged first by current i 1l (approx. 0.5 ma, for extended ringing suppression time). as soon as the voltage at pin 3 reaches the level v 3l (2.5 v), the charging current is switched to the higher value i 1h (approx. 1 ma, for normal ringing suppression time). this current flows until the capacitor?s voltage reaches 3.5 v. the charge time tc1 is : for proper operation of the special internal anti- jitter circuit, tc1 (rising time for i 1h only) should have the same value as the resonance time ?tr? of the power circuit ( figure 7 ). after charging c 1 up to 3.5 v the current source is disconnected and c 1 is discharged by resistor r 1 . the voltage v 1 at pin 1 is applied to the off-time comparator (oftc). the other input of oftc is the control voltage. the value of the control voltage at the input of oftc is limited to a minimum of 2 v (for stable frequency at very light load). the on- time flip flop (ontf) is set, if the output of oftc is high 1) and the voltage v 3 at pin 3 falls below 25 mv (zero crossing signal is high). this ensures switching on of the power transistor at minimum voltage. if no zero crossing signal is coming into pin 3, the power transistor is switched on after an additional delay until v 1 falls below 1.5 v (see figure 6 , oftcd). as long as v 1 is higher than the limited control voltage, ontf is disabled to suppress wrong zero crossings of v 3 , due to parasitic oscillations from the transformer after switch-off. the discharge time of c 1 is a function of the control voltage. 1) i.e. v 1 is less than the limited control voltage. . control voltage output power off-time td1 1.5 - 2 v low constant (td1 max. ), const. frequency stand by 2 - 3.5 v medium decreasing 3.5 - 5 v high free running, switch-on at first minimum i mprimary 4v v 11 3 ? ? () r 2 c 2 l primary ------------------------------------------------------------ = tc1 c 1 1,5 v 1ma -------------------------
tda 16846/16846-2 tda 16847/16847-2 version 2.0 1 1 31 jul 2003 if the control voltage is below 2 v (at low output power) the ?off-time? is maximum and constant during the discharge time td1, v1 must not fall below the limit v 1l , otherwise the function is not guaranteed. figure 6 off-time-circuit td1 max 056 , r 1 c 1
tda 16846/16846-2 tda 16847/16847-2 2 version 2.0 12 31 jul 2003 figure 7 pulse diagram of off-time-circuit figure 8 shows the converters switching frequency as a function of the output power. figure 8 load dependent frequency curve
tda 16846/16846-2 tda 16847/16847-2 2 version 2.0 13 31 jul 2003 error amplifier ea / soft-start (pin 3, pin 4) figure 9 shows the simpl ified error ampli fier c ircuit. the positive input of the error amplifier (ea) is the reference voltage 5 v. the negative input is the pulsed output voltage from the auxiliary winding, divided by r 31 and r 32 . the capacitor c 3 is dimensioned only for delaying zero crossings and smoothing the first spike after switch- off. smo othing of the regulation vo l tage is done wit h the soft s tart capacitor c 4 at pin 4. during start up c 4 is charged with a current of approx. 2 a (soft start). for primary regulation c 4 is charged and discharged with pulsed currents. figure 10 shows the voltage diagrams of the error amplifier circuit. figure 9 error amplifier figure 10 regulation pulse diagram
tda 16846/16846-2 tda 16847/16847-2 version 2.0 14 31 jul 2003 fixed frequency and synchronization circuit syn (pin 7) figure 11 shows the fixed frequency and synchronization circuit. the circuit is disabled when pin 7 is not connected or connected to pin 9 (vref, to avoid noise sensitivity). with r 7 and c 7 at pin 7 the circuit is working. c 7 is charged fast with approx. 1 ma and discharged slowly by r 7 ( figure 11 ). the power transistor is switched on at beginning of the charge phase. the switching frequency is (charge time ignored) : when the oscillator circuit is working the fold back point correction is disabled (not necessary in fixed frequency mode). ?switch on? is only possible when a ?zero crossing? has occurred at pin 3, otherwise ?switch-on? will be delayed ( figure 12 ). figure 11 synchronization and fixed frequency circuit f 08 , r 7 c 7 --------------
tda 16846/16846-2 tda 16847/16847-2 version 2.0 15 31 jul 2003 figure 12 pulse diagram for fixed frequency circuit synchronization mode is also possible. the synchronization frequency must be higher than the oscillator frequency. figure 13 ext. synchronization circuit
tda 16846/16846-2 tda 16847/16847-2 version 2.0 16 31 jul 2003 3 protection functions the chip has several protection functions: current limiting see ?primary current simulation pcs (pin 2) / current limiting? and ?fold back point correction pvc (pin 11)?. over- and undervoltage lockout ov/svc (pin 14) when v 14 at pin 14 exceeds 16.5 v, e. g. due to a fault in the regulation circuit, the error flip flop err is set and the output driver is shut-down. when v 14 goes below the lower svc threshold, err is reset and the driver output (pin 13) and the soft-start (pin 4) are shut down and actively held low. primary voltage check pvc (pin 11) when the voltage v 11 at pin 11 goes below 1 v the error flip flop (err) is set. e.g. a voltage divider from the rectified mains at pin 11 prevents high input currents at a too low input voltage. free usable fault comparator fc1 (pin 10) when the voltage at pin 10 exceeds 1 v, the error flip flop (err) is set. this can be used e. g. for mains overvoltage shutdown. free usable fault comparator fc2 (pin 6) when the voltage at pin 6 exceeds 1.2 v, the error flip flop (err) is set. a resistor between pin 9 (ref) and ground is necessary to enable this fault comparator. voltage dependent ringing suppression time during start-up and short-circuit operation, the output voltage of the converter is low and parasitic zero crossings are applied for a longer time at pin 3. therefore the ringing suppression time tc1 (see ?off-time circui t otc (pin 1)?) is extended with a factor of 2.2 at a low output voltage. the voltage at pin 1 must not fall below the limit v 1l .
tda 16846/16846-2 tda 16847/16847-2 version 2.0 17 31 jul 2003 4 temporary high power circuit fc2, pmo, ref (pin 6, 8, 9, tda 16847-2) figure 14 shows the temporary high power circuit: figure 14 the temporary high power circuit (thpc) consists of two parts: firstly, a power measurement circuit is implemented: the capacitor c 8 at pin8 is charged with a constant current i 8 during the discharge time of the flyback transformer and grounded the other time. thus the average of the sawtooth voltage v 8 at pin 8 is proportional to the converters output power (at constant output voltages). the charge current i 8 for c 8 is set by the resistor r 9 at pin 9: i 8 =5v/ r 9
tda 16846/16846-2 tda 16847/16847-2 version 2.0 18 31 jul 2003 secondly, a high power shutdown comparator (fc2) is implemented: when the voltage v 6 at pin 6 exceeds 1.2 v the error flip flop (err) is set. the output voltage of the power measurement circuit (pin 8) is smoothed by r 8 / c 6 and applied to the ?high power shutdown? input at pin 6. the relation between this voltage v 6 and the output power of the converter p is approximately: v 6 ( p l secondary 5v)/( v out 2 c 8 r 9 ) l secondary : the transformers secondary inductance v out : the converters output voltage so the time constant of r 9 / c 8 for a certain high power shutdown level p sd is: r 9 c 8 ( p sd l secondary 4.2)/ v out 2 the converters high power shutdown level can be adjusted lower (by r 9 , c 8 ) than the current limit level (see ?current limiting?). thus because of the delay r 8 / c 6 , the converter can deliver maximum output power (current limit level) for a certain time (e. g. for power pulses like motor start current) and a power below the high power shutdown level for an unlimited time. this is of advantage because the thermal dimensioning of the power devices needs to be done for the lower power level only. once the voltage v 6 exceeds 1.2 v no more charging or discharging happens at pin 8. the voltage v 6 remains high due to the bias current out of fc2 and the converter remains switched-off. reset can be done either by plugging-off the supply from the mains or by a high value resistor r 6 ( figure 14 ). r 6 causes a reset every few seconds. when pin 9 is not connected or gets too little current (i9 < i9fc2), the temporary high power circuit is disabled.
tda 16846/16846-2 tda 16847/16847-2 version 2.0 19 31 jul 2003 5 electrical characteristics note: stress beyond the above listed values may cause permanent damage to the device. exposure to absolute maximum rated conditions for extended periods may affect device reliability. 5.1 absolute maximum ratings all voltages listed are referenced to ground (0 v, v ss ) except where noted. parameter symbol limit values unit remarks min. max. supply voltage at pin 14 v cc ?0.3 17 v ? voltage at pin 1, 4, 5, 6, 7, 9, 10 ? ? 0.3 6 v ? voltage at pin 2, 8, 11 ? ? 0.3 17 v ? startup current into pin 2 i 2 1ma voltage at pin 3 current into pin 3 rzi ?10 6v ma v 3 < ? 0.3 v current into pin 9 i ref ?1 ? ma ? current into pin 13 i out ? 100 100 ma ma v 13 > v cc v 13 < 0 v esd protection ? ? 2 kv mil std 883c method 3015.6, 100 pf, 1500 storage temperature t stg ? 65 125 c? operating junction temperature t j ? 25 125 c? thermal resistance junction-ambient r thja ? 110 k/w p-dip-14-3 soldering temperature ? ? 260 c? soldering time ? ? 10 s ?
tda 16846/16846-2 tda 16847/16847-2 version 2.0 20 31 jul 2003 5.2 characteri stics unless otherwise stated, ? 25 c< t j < 125 c, v cc =12v parameter symbol limit values unit test condition min. typ. max. supply voltage and startup circuit vcc (pin 14) overvoltage threshold v 14 ov 15.7 16.5 17.1 v turn-on threshold v 14 on 14.5 15 15.5 v ? turn-off threshold v 14 off 7.5 8 8.5 v ? delta-ov- v 14 on ?0.5??v? supply current, off i 14off ?40100 a v cc = v 14 on -100 mv supply current, on i 14on ? 5 8 ma output low primary current simulation pcs (pin 2) / current limiting basic value v 2 1.45 1.5 1.55 v i 2 = 100 a peak value v 2 4.85 5 5.15 v v 11 = 1.2 v discharge current i 2dc 0.6 1.0 2.5 ma v 2 = 3 v bias current pin 2 ? ? 1.0 ? 0.3 ? a v 2 = 2 v fold back point correction pvc (pin 11) peak value v 5 3.8 4.1 4.3 v v 11 = 4.5 v bias current pin 11 ? ? 1.0 ? 0.3 ? a v 11 = 1.5 v off-time circuit otc (pin 1) charge current i 1h 0.9 1.1 1.4 ma v 3 > v 3l charge current i 1l 0.35 0.5 0.65 ma v 3 < v 3l peak value v 1p 3.38 3.5 3.62 v ? basic value 1 v 1b1 1.9 2 2.1 v ? basic value 2 v 1b2 1.44 1.5 1.58 v ? v 1 lower limit v 1l 80 140 mv bias current pin 1 ? ? 1.1 ? 0.4 ? a v 1 = 2.2 v
tda 16846/16846-2 tda 16847/16847-2 version 2.0 21 31 jul 2003 zero crossing input rzi (pin 3) zero crossing threshold (pin 3) 15 25 35 mv ? delay to switch-on t 3d 250 350 460 ns ? bias current pin 3 ? ?2 ? 1.2 ? a v 3 = 0 v error amplifier input rzi (pin 3) input threshold (pin 3) v eath 4.85 5 5.15 v ? low voltage threshold (pin 3) v 3l 2.4 2.5 2.6 v ? bias current pin 3 ? ? ? 0.9 ? a v 3 = 3 v softstart and regulation voltage src (pin 4) soft-start charge current (pin 4) i 4chs ? 2.5 ? 1.8 ? 1.2 a v 4 = 2 v charge current pin 4 i 4ch -0.9 -0.7 -0.5 ma discharge current pin 4 i 4dch 0.9 1.4 1.9 ma opto coupler input oci (pin 5) input voltage range (tda 16846, tda 16847) v 5 0.3 ? 6 v ? input voltage range (tda 16846-2, tda 16847-2) v 5 0?6v? pull high resistor to v ref r 1 15 20 28 k ? 5.2 characteristics (cont?d) unless otherwise stated, ? 25 c< t j <125 c, v cc =12v parameter symbol limit values unit test condition min. typ. max.
tda 16846/16846-2 tda 16847/16847-2 version 2.0 22 31 jul 2003 fixed frequency and synchronization circuit syn (pin 7) charge current i 7 -0.9 -1.3 -1.6 ma ? upper threshold v 7h 3.4 3.6 3.7 v ? lower threshold v 7l1 1.53 1.6 1.67 v ? input voltage range v 7l2 0.4 6 v ? bias current pin 7 ? ? 2.4 ? 1.8 ? 1.1 a v 7 =4 v primary voltage check pvc (pin 11) threshold v 11 0.95 1 1.06 v ? reference voltage ref (pin 9) voltage at pin 9 v 9 4.8 5 5.15 v i 9 =?100 a current to enable fc2 i 9fc2 ?18 ?7 a 5.2 characteristics (cont?d) unless otherwise stated, ? 25 c< t j < 125 c, v cc =12v parameter symbol limit values unit test condition min. typ. max.
tda 16846/16846-2 tda 16847/16847-2 version 2.0 23 31 jul 2003 note: the listed characteristics are ensured over the operating range of the integrated circuit. typical characteristics specify mean values expected over the production spread. if not otherwise specified, typical characteristics apply at t a = 25 c and the given supply voltage. fault comparator fc2 (pin 6) hpc threshold v 6 1.12 1.2 1.28 v ? bias current pin 6 ? ? 1.0 ? 0.3 0.1 a v 6 =0.8v fault comparator fc1 (pin 10) threshold v 10 0.95 1 1.06 v ? bias current pin 10 ? 0.35 0.65 0.95 a v 10 =0.8v power measurement output pmo (pin 8, only tda 16847, tda 16847-2) charge current pin 8 i 8 ?110 ?100 ?90 a i 9 =?100 a output driver out (pin 13) output voltage low state v 13 low 1.1 1.8 2.4 v i 13 = 100 ma output voltage high state v 13 high 9.2 10 11 v i 13 = ? 100 ma output voltage during low v 14 (tda 16846, tda 16847) v 13 aclow 0.8 1.8 2.5 v i 13 = 10 ma, v 14 = 7 v output voltage during low v 14 (tda 16846-2, tda 16847-2) v 13 aclow 0.5 1 1.5 v i 13 = 10 ma, v 14 = 7 v rise time ? 30 50 100 ns c 13 = 1 nf, v 13 =2?8v fall time ? 102050ns c 13 = 1 nf, v 13 =2?8v 5.2 characteristics (cont?d) unless otherwise stated, ? 25 c< t j <125 c, v cc =12v parameter symbol limit values unit test condition min. typ. max.
tda 16846/16846-2 tda 16847/16847-2 version 2.0 24 31 jul 2003 figure 15 circuit diagram for application with pfc
tda 16846/16846-2 tda 16847/16847-2 version 2.0 25 31 jul 2003 figure 16 circuit diagram for standard application
tda 16846/16846-2 tda 16847/16847-2 version 2.0 26 31 jul 2003 figure 17 circuit diagram for application with temporary high power circuit
tda 16846/16846-2 tda 16847/16847-2 version 2.0 27 31 jul 2003 package outlines p-dip-14-3 (plastic dual in-line package) gpd05584 sorts of packing package outlines for tubes, trays etc. are contained in our data book "package information". dimensions in mm
tda 16846/16846-2 tda 16847/16847-2 version 2.0 28 31 jul 2003 p-dso-14-3 (plastic dual in-line package) sorts of packing package outlines for tubes, trays etc. are contained in our data book "package information". dimensions in mm
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